1. Field of the Invention
The present invention relates generally to semiconductor device design, and more particularly, to a modular test controller with Built-In Self-Test (BIST) functionality for testing an embedded DRAM (eDRAM) circuit and a method for manufacturing the same.
2. Description of the Related Art
To reach a fast product ramp up and a high yield, any standard DRAM or embedded DRAM circuit needs intensive testing. Each DRAM contains redundant wordlines and bitlines to enable reparability of defective memory cells. Most of the commonly used DRAM tests are used to find all possible storage cell failures and then collect all these failures in a so-called fail bit map. With this fail bit map, an external tester calculates the best usage of the on-chip redundancy.
DRAMs embedded into ASICs (Application Specific Integrated Circuits) require different test strategies than standalone commodity DRAMs. Embedded DRAMs (eDRAM) often contain a test controller and/or a BIST (Built-In Self-Test) circuit to simplify the testing. Commodity DRAM's normally do not contain any additional test circuits and are tested through a memory tester, whereas eDRAM's are tested together with the other ASIC circuit parts through a logic tester.
FIG. 7 illustrates an example of a typical implementation of a test system for testing an ASIC (Application Specific Integrated Circuit) 701 containing an embedded DRAM 703 (eDRAM). The eDRAM is testable through an on-chip test controller 702 with BIST functionality. The BIST logic circuitry contains test programs and redundancy algorithms to decide if the eDRAM 703 passed or failed the test, i.e., whether the eDRAM is good or bad. An external logic tester 700 could operate this test controller 702 by serially scanning information in (via scan in data line 706), and out (via scan out data line 708) of the chip. Subsequently, the test controller 702 will issue a pass/fail signal via line 710.
Developing a test flow and testing an eDRAM could be a very difficult and expensive task. Because of its nature, the eDRAM isn't standardized and could be designed with a wide variety of options (e.g., I/O width, SRAM, SDRAM interface, etc.), best suited to fit a certain ASIC product/application. Each of these eDRAM “flavors” would need it's own testflow developed and it's own dedicated BIST/test controller developed. Both of these tasks are time consuming and cost intensive, especially for “time-to-market” sensitive products like ASIC's.
Additionally, the conventional configuration, shown in FIG. 7, does not allow a fail bit map of the eDRAM to be collected. Furthermore, the BIST is hardcoded and interfaces only to one specific eDRAM, and thus, could not be used with a different interface or on a next generation eDRAM without extensive rework.
Accordingly, it would be desirable and highly advantageous to have a modular test controller with BIST functionality for embedded DRAMs on an ASIC so a core BIST circuit, with proven testing algorithms, can be used in multiple products/applications.